In forming conventional through-via (TV) processes for three dimensional (3D) arrangements using semiconductor wafers, low-temperature oxidation is adopted to line through silicon vias (TSVs) with a thin oxide layer to isolate the TSV's from the wafer. Due to the high aspect ratio of a typical TSV, the stress in the trench corners at the bottom of the vias in the wafer may cause oxide cracks, and when the metallization is subsequently formed, metal extrusions (such as copper or Cu extrusions) may form. These cracks and extrusions negatively impact device reliability and performance.
In a particular application of TVs, during fabrication of back side illumination (BSI) CMOS image sensor (CIS) devices, a carrier wafer may be wafer bonded to an active device wafer using wafer bonding. For example, a silicon wafer may be the active device wafer and may have many integrated circuits formed therein, where the integrated circuits are each CIS devices, the integrated circuits each having an array of photodiodes. Several metallization layers may be formed in layers of dielectric material formed over the front side of the active device wafer.
On the opposing back side of the active device wafer, for a back side illuminated (BSI) image sensor, light will allowed to fall on the photodiodes of the BSI CIS devices, and color filter array (CFA) material may be formed over the back side of the active device wafer and aligned with the photodiodes to form color pixels. Microlens (ML) material may be arranged over the CFA material to further increase the light reception. A glass layer may be bonded to the back side of the active device wafer to protect the CIS devices. Materials used for the CFA, ML and bonding material may be particularly sensitive to high temperature processes.
To complete these BSI CIS devices, in a wafer level process, the carrier wafer such as a silicon carrier wafer may be bonded over the front side of the active device wafer. In the conventional approach, TVs may be etched into and through the semiconductor carrier wafer, creating via openings that extend through the carrier wafer. The TVs may be extended to expose a portion of the uppermost metallization layers formed over the active device wafer. A copper conductive material or other conductor may be deposited in the through-vias, and the conductors create electrical paths extending through the carrier wafer.
The silicon etch processes to form TSVs in the carrier wafer, and the related thermal and mechanical stresses that occur, may cause cracks in the upper dielectric layers of the active device wafer. Cracks may form in the liner oxide layer in the vias. Further, copper extrusions may form into these cracks during the copper deposition processes. The processes used in forming the TSVs in the carrier wafer may require high temperature processes. The high temperatures used in these processes may further create undesirable thermal stresses on the devices in the active device wafer and on other materials used.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.